HOMEPLL Synth Designer

System

Loop filter

Schematic
C1 R1 C2 R2 C3
Generates a starting loop filter meeting target loop bandwidth and phase margin.

Noise models

Interpolation is log-frequency, linear in dB.
PFD/CP FOM is interpreted as a normalized PLL phase-noise floor: FOM + 10·log10(fPFD) + 20·log10(N), then shaped by the closed-loop tracking response. Divider floor inputs are additive noise at their divider outputs.

Quick checks

Unity gain (Hz)
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Phase margin (deg)
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Loop BW −3 dB (Hz)
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Closed-loop stability
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Notes:
  • After your design is optimised, use the Integrated Phase Noise tool for further analysis.
  • This tool uses a standard linear charge-pump PLL model and a 3rd-order passive filter network via complex nodal analysis.

Total phase noise preview

Adjust inputs on the left and click Update. Use the integration band to compute integrated total phase noise (dBc) over offset frequency.
Offset (Hz) Total (dBc/Hz)

Loop responses

Red dotted lines show the exact finite loop-filter poles and zero; the pole at the origin is listed but cannot be shown on a logarithmic frequency axis.

Phase noise & FM response

Offset (Hz) Total (dBc/Hz) PFD/CP normalized FOM contribution (dBc/Hz) Reference (dBc/Hz) VCO (dBc/Hz) Dividers (dBc/Hz)

Time-domain response (digital PFD behavior)

The frequency step is generated from the exact fourth-order linear closed-loop transfer function. The PFD/charge-pump trace is a compact digital illustration derived from the resulting divided-frequency phase error; it shows only the first limited set of PFD cycles when the full settling interval would contain too many pulses.

Step definition

Time-domain metrics

Computed from the exact fourth-order linear closed-loop transfer function using numerical state-space integration.
Metric Value (ms)

Notes, rules of thumb, and how to use the tool

Workflow

  1. Enter your system parameters (fRef, fOut, R, Icp, Kv) and target stability (loop BW and phase margin).
  2. Click Synthesize to generate a first-pass passive loop filter (R1, R2, C1, C2, C3).
  3. Optionally tweak the filter values. Click Update to recompute outputs and plots.
  4. Inspect open/closed-loop response, then phase noise. Use the integration band to compute integrated phase noise.
  5. Use the time-domain tab to sanity-check settling behavior for a frequency step.

Loop-shaping rules of thumb (industry practice)

  • Target phase margin: 45–60° is a common practical range. Higher PM improves ringing/settling but can reduce suppression at some offsets.
  • Target loop bandwidth: typically between fPFD / 20 and fPFD / 5, trading off settling time and noise + spurs.
  • Unity gain vs. closed-loop bandwidth: for typical charge-pump PLLs, −3 dB closed-loop bandwidth is often ~0.3–0.7× unity gain frequency, depending on damping.
  • Place the main zero below unity gain: a common start is fz ≈ fUGF/3 to fUGF/6 to add phase lead near crossover.
  • Keep the “extra” pole above unity gain: often fp,HF ≈ 5× to 15× fUGF so it doesn’t steal phase margin at crossover but still attenuates high‑frequency noise/spurs.
  • PFD frequency guidance: higher fPFD generally allows wider loop bandwidth and lower in-band divider contribution, but raises reference spur management requirements.
  • Don’t chase extreme bandwidth: a too-wide loop can increase reference feedthrough/spurs and may stress VCO tuning/supply/CP compliance.
  • Noise trade: widen the loop if VCO noise dominates near offsets of interest; narrow the loop if reference/divider noise dominates in-band.
  • Check headroom: ensure the control voltage stays within VCO tuning range for your step and that CP current and R values don’t cause unrealistic voltages.

Reading the plots

  • Open-loop gain/phase: crossover at 0 dB; phase margin is 180° + phase at crossover.
  • Closed-loop tracking (G/(1+G)): shows how reference/divider noise is transferred to the output.
  • FM suppression (1/(1+G)): shows how VCO noise is suppressed in-band.
  • Red dotted lines: exact finite loop-filter pole/zero frequencies derived from the transfer-function denominator/numerator.
  • Phase noise integration: the displayed integral is single-sideband (SSB). RMS phase error uses twice the SSB integral, and RMS jitter is RMS phase error divided by 2πfOUT.

Practical caveats

  • This is a linear model: it does not include cycle slipping, CP non-idealities, saturation, discrete-time effects, spur modeling, or ΣΔ quantization noise unless you approximate them via noise floors/profiles.
  • The listed filter poles/zero are exact for the passive network. Closed-loop stability is checked separately from the fourth-order characteristic polynomial. Frequency-domain analysis may extend to high offset frequencies. A bench-design warning is shown only when the actual loop crossover/bandwidth is too high relative to fPFD, where sampled-PFD effects can materially affect loop behaviour.