Generates a starting loop filter meeting target loop bandwidth and phase margin.
Noise models
Interpolation is log-frequency, linear in dB.
Quick checks
Unity gain (Hz)
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Phase margin (deg)
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Loop BW ~ (Hz)
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Notes:
After your design is optimised, use M0LNB's Integrated Phase Noise tool for further analysis.
This tool uses a standard linear charge-pump PLL model and a 3rd-order passive filter network via complex nodal analysis.
Total phase noise preview
Adjust inputs on the left and click Update. Use the integration band to compute integrated total phase noise (dBc) over offset frequency.
Offset (Hz)
Total (dBc/Hz)
Loop responses
Red dotted lines in the plot show these approximate breakpoints.
Phase noise & FM response
Offset (Hz)
Total (dBc/Hz)
Loop filter / PFD path (dBc/Hz)
Reference (dBc/Hz)
VCO (dBc/Hz)
Dividers (dBc/Hz)
Time-domain response (digital PFD behavior)
The plots below show a frequency step and the corresponding digital PFD/charge-pump pulses (UP/DN current pulses at the PFD rate),
which is how most modern PLLs behave. The PFD output is shown as a signed current (+Icp for UP, −Icp for DN) with pulse width proportional
to the instantaneous phase error (clipped to one reference period).
Step definition
Time-domain metrics
Computed from the simulated step response (illustrative model; we will refine accuracy next).
Metric
Value (ms)
Notes, rules of thumb, and how to use the tool
Workflow
Enter your system parameters (fRef, fOut, R, Icp, Kv) and target stability (loop BW and phase margin).
Click Synthesize to generate a first-pass passive loop filter (R1, R2, C1, C2, C3).
Optionally tweak the filter values. Click Update to recompute outputs and plots.
Inspect open/closed-loop response, then phase noise. Use the integration band to compute integrated phase noise.
Use the time-domain tab to sanity-check settling behavior for a frequency step.
Loop-shaping rules of thumb (industry practice)
Target phase margin: 45–60° is a common practical range. Higher PM improves ringing/settling but can reduce suppression at some offsets.
Target loop bandwidth is typically between fPFD / 20 and fPFD / 5, trading off settling time and noise + spurs.
Unity gain vs. closed-loop bandwidth: for typical charge-pump PLLs, −3 dB closed-loop bandwidth is often ~0.3–0.7× unity gain frequency, depending on damping.
Place the main zero below unity gain: a common start is fz ≈ fUGF/3 to fUGF/6 to add phase lead near crossover.
Keep the “extra” pole above unity gain: often fp,HF ≈ 5× to 15× fUGF so it doesn’t steal phase margin at crossover but still attenuates high‑frequency noise/spurs.
PFD frequency guidance: higher fPFD generally allows wider loop bandwidth and lower in-band divider contribution, but raises reference spur management requirements.
Don’t chase extreme bandwidth: a too-wide loop can increase reference feedthrough/spurs and may stress VCO tuning/supply/CP compliance.
Noise trade: widen the loop if VCO noise dominates near offsets of interest; narrow the loop if reference/divider noise dominates in-band.
Check headroom: ensure the control voltage stays within VCO tuning range for your step and that CP current and R values don’t cause unrealistic voltages.
Reading the plots
Open-loop gain/phase: crossover at 0 dB; phase margin is 180° + phase at crossover.
Closed-loop tracking (G/(1+G)): shows how reference/divider noise is transferred to the output.
FM suppression (1/(1+G)): shows how VCO noise is suppressed in-band.
Red dotted lines: approximate pole/zero break frequencies derived from the component values.
Phase noise integration: integrated total PN is computed by integrating 10^(L(f)/10) over the selected offset band and reporting 10·log10(integral) in dBc.
Practical caveats
This is a linear model: it does not include cycle slipping, CP non-idealities, saturation, discrete-time effects, spur modeling, or ΣΔ quantization noise unless you approximate them via noise floors/profiles.
Pole/zero locations are shown as breakpoint approximations; the exact closed-loop poles depend on the full loop dynamics.