Design target: approximately 25-35 V/V overall midband gain with a 47 kOhm load, using deliberate emitter degeneration rather than maximum possible transistor gain.
Run .op and record both Q points. Estimate stage 2 input resistance and include it in stage 1 collector loading. Then calculate each stage gain and multiply, including source attenuation.
AC: identify lower and upper -3 dB frequencies and compare with coupling/bypass and Miller estimates. Transient: 20 mV peak at 10 kHz should produce an unclipped output of order several hundred millivolts peak. Increase input until clipping and identify which stage runs out of headroom first.
