Ch07 Topic 09 - MOSFET Capacitances and Miller Effect
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Purpose
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Compare identical common-source stages with different gate-drain capacitance to isolate the Miller-effect bandwidth penalty.

Open in RFspice
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1. Open ACDSPICE_Ch07_T09_Miller_Effect.rfspice.json.
2. Run the analyses already entered in the Analysis box.
3. Plot the nodes/currents named in expected_results.txt.
4. Compare the result with the hand calculation before changing values.

Files
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- ACDSPICE_Ch07_T09_Miller_Effect.rfspice.json: native RFspice schematic/project JSON.
- ACDSPICE_Ch07_T09_Miller_Effect.cir: corresponding plain SPICE netlist.
- expected_results.txt: hand checks and expected trends.
- models/: local model library used by this worked example.

Model note
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The FET models supplied with this course are educational representative models. They are intended to teach parameter-to-circuit relationships. Threshold voltage, IDSS, transconductance and capacitance vary substantially in real devices, so use the selected manufacturer's current datasheet and production SPICE model for final hardware correlation.
